In wideband telecommunication applications, there is a need for high speed analogue-to-digital converters (ADCs, or AD converters) with a high SNDR (Signal to Noise and Distortion Ratio).
By using parallelism, a fast ADC can be constructed from several slow sub-ADCs, controlled by a multi-phase clock. "Time Interleaved Converter Arrays", Black et al., IEEE Journal of Solid State Circuits, Vol SC-15, No 6, pp 1022-29, December 1980, discloses a high speed weighted capacitor ADC using parallel or time interleaving technique.
Several error sources limit the performance of parallel ADCs. Different offsets and different gains in the sub-ADCs generate distortion. Another more troublesome error source is the sampling phase skew in the parallel channels, which introduces distortion. The sampling instants must be equally spaced between two successive sub-ADCs in order to re-construct the signal in the digital domain. The difference in the distance of sampling instants between two successive sub-ADCs is called the phase skew. The phase skew arises due to the fact that the sampling instant is controlled by different clock phases in different places. Any noise and unbalanced parasitic contribute to the phase skew.
The relationship between SNDR and the phase skew has been discussed in "Digital Spectra of Nonuniformly Sampled Signals: Fundamentals and High Speed Waveform Digitizers", IEEE T. Instrumentation and measurement, Vol. 37, No 2, p 245-51, June 1988.
"An 8-b 85-Ms/s parallel Pipeline A/D Converter in 1 .mu.m CMOS", Conroy et al., IEEE J. Solid State Circuits, Vol 28, No 4, pp 44754, April 1993, discloses a four channel ADC in CMOS with a timing mismatch approximated from measurements to be about 25 ps. This is not adequate for wideband telecommunication applications, where a high SNDR at high signal frequencies is required.
One way to overcome this is to place a track-and-hold amplifier at the input. This is not desirable in that it demands a high-gain operational amplifier driving a large capacitive load at a very high frequency.
U.S. Pat. No. 5,247,301 to Yahagi et al. discloses a two-step or sub-flash type ADC, using a common analogue input switch in series with a second analogue switch to reduce the timing error. Independent of the number of sub-converters, the clock signal for the analogue input switch has the same frequency as the control signals for all the sample-and-hold switches. All the switches are turned on by the same phase (only the turning-off of the common switch leads the turning-off of other switches). The common switch is at the input of the device, therefore, due to the implementation of the switch (e.g. a MOS transistor), the turning of instant is a function of the input voltage. Due to the charge redistribution of a MOS switch, another source of error, the charge injection error, is introduced. The signal-independent part, i.e. the charge injection caused offset voltage, can be compensated to a certain extent by using a compensator as disclosed in FIGS. 3, 4 and 5 of U.S. Pat. No. 5,247,301. But the signal-dependent charge injection error remains to be compensated for. The signal-dependent turning-off instant and signal-dependent charge injection error introduce very strong distortions in any ADC, and thus this device is not applicable to any high dynamic performance ADC.